An important aspect of logic circuit design is "timing-driven" optimization, which attempts to improve the speed at which signals at circuit inputs will arrive at circuit outputs. In contrast to architectural optimization techniques, such as those that focus on faster algorithms, timing-driven optimization focusses on changes to individual circuit elements. Timing-driven optimization may involve a number of restructuring techniques, such as gate input reordering, transistor sizing, buffer insertion, and in BiCMOS circuits, selection and deselection of BiCMOS elements.
Timing-driven optimization includes timing analysis of various restructuring choices to determine the desirability of one choice over another. Typically, timing evaluations are incremental, in the sense that every change to the characteristics of any element in the design invalidates the design's currently calculated timing characteristic and requires a timing recomputation before another element is optimized.
In existing optimization methods, these incremental timing recomputations can be computationally expensive. In some methods, each local optimization requires recomputation of delays at all preceding and succeeding elements.
A need exists for a method of performing timing analysis during timing-driven circuit optimization that reduces computation time.